The present invention relates to a semiconductor integrated circuit which is automatically designed by using a computer and, more particularly, to a large scale integrated circuit (LSI) manufactured using an aluminum wiring multilayer technique.
Automatic design of LSIs of this type adopts a so-called polycell technique. This technique is described in, e.g., "IEEE Journal of Solid-State Circuits" CH1726-9/82 pp. 111-114, 1982, and in Japanese Patent Application No. 51-74627 by the same applicant as of the present invention.
FIG. 1 schematically shows a plan view of an LSI pattern designed in accordance with the polycell technique. Each of the wiring regions (channel regions) 12-1, 12-2, . . . is disposed between each two adjacent cell arrays 11-1, 11-2, 11-3, . . . Each of the cell arrays 11-1, 11-2, 11-3, . . . is constructed by unit cells (logic circuit cells) 11A, 11B, 11C, . . . including various function circuits. These unit cells 11A, 11B, 11C, . . . are connected through the above channel regions 12-1, 12-2, . . . When wiring must be formed across the cell arrays, it is formed in the gaps 13 (through regions) between each two adjacent unit cells.
FIGS. 2A and 2B respectively show pattern structures of an inverter circuit as an example of the unit cells 11A. FIG. 2A is a pattern plan view, and FIG. 2B is a sectional view taken along a line X--X' of FIG. 2A. Impurity diffusion regions 15-1 and 15-2 as source and drain regions of a MOS transistor are formed in a major surface of semiconductor substrate 14. A gate insulating film 16 is formed on the semiconductor substrate 14 between the impurity diffusion regions 15-1 and 15-2. A gate electrode 17 is formed on the gate insulating film 16. Aluminum wiring layers 18-1 and 18-2 are formed on the impurity diffusion regions 15-1 and 15-2, respectively, so as to form contacts. A field oxide film 19 is selectively formed on the semiconductor substrate 14. An output wiring layer 20 of polysilicon is formed on the field oxide film 19. The wiring formed in the through regions 13 is formed by a polysilicon layer P2 on the field oxide film 19, as shown in FIG. 2C. Wiring layers 22-1 and 22-2, as shown in FIG. 2A, for supplying a power source voltage to the unit cells are formed of aluminum layers.
Since the unit cells with the above structure are laterally (or longitudinally) aligned so as to construct the cell array, in the semiconductor integrated circuit device shown in FIG. 1, the wiring layers parallel to the cell arrays 11-1, 11-2, 11-3, . . . (aligned along the X direction) are formed of aluminum wiring layers A1 to A3 and the wiring layers perpendicular thereto (Y direction) are formed of polysilicon wiring layers P1 to P4. Note that the aluminum wiring layers A1 to A3 and the polysilicon wiring layers P1 to P4 are connected by contact portions 10-1 to 10-5.
The above structure has the following disadvantages.
First, high speed operation is prevented by the resistance of the polysilicon wiring layer. This is because the sheet resistance of a polysilicon film is several tens of ohms/.quadrature. and is 100 times or more than that of the aluminum film. This wiring resistance causes a transfer delay of signals. The transfer delay is increased when the length of the through wiring layer P2 formed of polysilicon is increased. When the output wiring layer P1 is formed of polysilicon, the transfer delay of signals is further increased by the resistance thereof. As shown in FIG. 3, in the circuit arrangement having four fan-outs with respect to an inverter circuit 23, assume that an output resistance of the output wiring layer is represented by R0, input resistances of the input wiring layers connected to the next stage are represented by R1 to R4, a load capacitance of the wiring layers is represented by C0, load capacitances of the gates of the next stage are represented by C1 to C4, signal transmission time from a point A to a point C is represented by T1, and signal transmission time from a point B to a point C is represented by T2. The times T1 and T2 are respectively approximated by using the following equations (1) and (2): EQU T1=C0.multidot.R0+C1.multidot.R1 . . . (1) EQU T2=C1.multidot.R1 . . . (2)
where in the case of the arrangement shown in FIG. 1, since R0&gt;&gt;R1 and C0&gt;&gt;C1 are established, relation T1&gt;T2 is also established. This means the influence of the output resistance R0 and the load capacitance C0 with respect to the signal transmission time is much larger than that of the resistance R1 and the capacitance C1. Particularly, in the arrangement shown in FIG. 1, due to the presence of the polysilicon through wiring layer P2, the output resistance cannot be decreased. In addition, when the number of fan-outs is increased, the load capacitance C0 becomes large, thus preventing high speed operation.
Second, when the wiring layer P2 is formed across the cell arrays 11-2, through regions 13 are required between each two adjacent unit cells. This prevents high integration.
Third, when positions of the through wiring layers P2 are determined, positions of the unit cells are undesirably shifted. Thus, neither the optimum position of the through wiring layer P2 nor the optimum algorithm of the wiring layers between the unit cells can be achieved. As a result, the wiring layers cannot be highly integrated. This can be easily understood from a comparison between wiring algorithms in the case wherein the positions of the unit cells are not shifted and in the case wherein the positions of the unit cells are shifted every time the through wiring layers are formed in automatic wiring.
As described above, in a conventional semiconductor integrated circuit device manufactured in accordance with the polycell technique, a high-speed and highly integrated device cannot be obtained.